1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device having a so-called WCSP (Wafer-Level Chip Size Package) structure, and to a manufacturing apparatus used in this manufacturing method, in particular to an optical exposure apparatus.
2. Description of the Related Art
A package having a size equal to a single semiconductor chip cut from the semiconductor wafer is generally known as a CSP (Chip-Size Package). The CSP obtained when resin sealing is applied over a semiconductor chip formed on a semiconductor wafer in the semiconductor wafer state is called a WCSP.
A WCSP is obtained by separation of a structure which includes a plurality of semiconductor devices formed in a matrix on a semiconductor wafer using wafer processes.
In a WCSP manufacturing process, when forming protruding electrodes (also called electrode posts), for example a negative resist material is used to form a resist pattern for a plating process over the entire wafer surface on which a rewiring layer is formed. In this resist pattern for a plating process, aperture portions are formed at positions at which protruding electrodes are to be formed. Those regions on the negative resist material (resist layer) which are not optically exposed by the exposure apparatus are removed to form aperture portions. Thus, the optical exposure process is performed using a mask to shield those regions on the resist layer in which protruding electrodes are to be formed.
Semiconductor devices are not formed along the periphery of the wafer. In the optical exposure process, a light shielding layer is formed covering the entire periphery of the wafer. After the optical exposure process, the UBM (Under Barrier Metal) layer (hereafter also simply called the conducting layer) in the peripheral region is caused to be exposed on the surface. Such technology is for example disclosed in Japanese Patent Kokai (Laid-open Application) No. 2001-156093.
There is another known technology. In order to expand the usable area of the wafer, optical exposure is applied on a peripheral region of positive resist provided on the entire wafer surface (see for example Japanese Patent Kokai No. 2-114628). As a result, there exists a contact portion in the peripheral region which is in contact with retaining claws used to hold the wafer, and the contact portion is also optically exposed.
As described above, in the conventional WCSP manufacturing methods the entirety of the wafer peripheral portion is optically exposed, so that the UBM film (conductive film) exposed at the surface in the wafer peripheral region is also plated in the protruding electrode formation process (plating process). In the plating process, the conductive film must be exposed at the surface as an electrode portion in the wafer peripheral region because it has to be electrically connected with the plating equipment. However, when a conductive film is exposed at the surface over the entire peripheral region, plating material is wasted in the plated film formed over the entire conductive film.
As disclosed in Japanese Patent Kokai No. 2-114628, if a mask is formed and a special optical exposure process is used to optically expose only the peripheral portion of the wafer, that is, if the process of forming the electrode portion for the plating process is a separate process, then the number of processes is increased. As a result, there tends to be an increase in the semiconductor device manufacturing costs.
Further, in the peripheral region near the outer perimeter of the semiconductor wafer, if the area of the UBM film exposed at the surface becomes large, there creates the possibility that a plated film may be formed in this region. When for example retaining the semiconductor wafer during the sealing process, stresses are concentrated in the region in which this plated film appears. This would result in damage to the semiconductor wafer.